//------------------------------------------------------------------------------
//
//  File: S3c2443.h
//
//  Copyright (C) 2007 Visual.Wei
//  Author: Wei Shuai <cpuwolf@sina.com>
//
//  Common Class for Device Driver Development
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA
//


#ifndef __H_S3C2443__
#define __H_S3C2443__



//------------------------------------------------------------------------------
//  Type: S3C2443_CLKPWR_REG
//
//  Clock and Power Management registers.
//

typedef struct 
{
    UINT32   LOCKCON0;           // 0x00    // MPLL lock time count register
    UINT32   LOCKCON1;           // 0x04    // EPLL lock time count register
    UINT32   OSCSET;             // 0x08
    UINT32   PAD1;               // 0x0C
    UINT32   MPLLCON;            // 0x10    // MPLL configuration register
    UINT32   PAD2;               // 0x14
    UINT32   EPLLCON;            // 0x18    // EPLL configuration register
    UINT32   PAD3;               // 0x1C
    UINT32   CLKSRC;             // 0x20
    UINT32   CLKDIV0;            // 0x24
    UINT32   CLKDIV1;            // 0x28
    UINT32   PAD4;               // 0x2C
    UINT32   HCLKCON;            // 0x30
    UINT32   PCLKCON;            // 0x34
    UINT32   SCLKCON;            // 0x38
    UINT32   PAD5;               // 0x3C
    UINT32   PWRMODE;            // 0x40
    UINT32   SWRST;              // 0x44        // Software reset control
    UINT32   PAD6;               // 0x48
    UINT32   PAD7;               // 0x4C
    UINT32   BUSPRI0;            // 0x50
    UINT32   PAD8;               // 0x54
    UINT32   BUSMISC;            // 0x58
    UINT32   SYSID;              // 0x5C
    UINT32   PWRCFG;             // 0x60
    UINT32   RSTCON;             // 0x64
    UINT32   RSTSTAT;            // 0x68
    UINT32   WKUPSTAT;           // 0x6C
    UINT32   INFORM0;            // 0x70
    UINT32   INFORM1;            // 0x74
    UINT32   INFORM2;            // 0x78
    UINT32   INFORM3;            // 0x7C
    UINT32   USB_PHYCTRL;               // 0x80
    UINT32   USB_PHYPWR;               // 0x84
    UINT32   USB_RSTCON;               // 0x88
    UINT32   USB_CLKCON;               // 0x8C
    UINT32   USB_TESTTI;               // 0x90
    UINT32   USB_TESTTO;               // 0x94


//    UINT32   CLKCON;                 // clock generator control register
//    UINT32   CLKSLOW;                // slow clock control register
//    UINT32   CLKDIVN;                // clock divider control register
//    UINT32	 CAMDIVN;				 // camera clock divider register

} S3C2443_CLKPWR_REG, *PS3C2443_CLKPWR_REG,  S3C2443_SYSCON_REG, *PS3C2443_SYSCON_REG;

typedef struct {
	UINT32 GPACDL;                  // Port A - offset 0
	UINT32 GPACDH;                  // Data

    UINT32 PAD1[2];

    UINT32 GPBCON;                  // Port B - offset 0x10
    UINT32 GPBDAT;                  // Data
    UINT32 GPBUDP;                   // Pull-up disable
    UINT32 PAD2;

    UINT32 GPCCON;                  // Port C - offset 0x20
    UINT32 GPCDAT;                  // Data
    UINT32 GPCUDP;                   // Pull-up disable
    UINT32 PAD3;
    
    UINT32 GPDCON;                  // Port D - offset 0x30
    UINT32 GPDDAT;                  // Data
    UINT32 GPDUDP;                   // Pull-up disable
    UINT32 PAD4;
    
    UINT32 GPECON;                  // Port E - offset 0x40
    UINT32 GPEDAT;                  // Data
    UINT32 GPEUDP;                   // Pull-up disable
    UINT32 PAD5;                 
    
    UINT32 GPFCON;                  // Port F - offset 0x50
    UINT32 GPFDAT;
    UINT32 GPFUDP; 
    UINT32 PAD6;
    
    UINT32 GPGCON;                  // Port G - offset 0x60
    UINT32 GPGDAT;
    UINT32 GPGUDP; 
    UINT32 PAD7;
    
    UINT32 GPHCON;                  // Port H - offset 0x70
    UINT32 GPHDAT;
    UINT32 GPHUDP; 
    UINT32 PAD8;

    UINT32 MISCCR;                  // misc control reg - offset 0x80
    UINT32 DCLKCON;                 // DCLK0/1 control reg
    
    UINT32 EXTINT0;                 // external interrupt control reg 0
    UINT32 EXTINT1;                 // external interrupt control reg 1
    UINT32 EXTINT2;                 // external interrupt control reg 2
    
    UINT32 EINTFLT0;                // reserved
    UINT32 EINTFLT1;                // reserved
    UINT32 EINTFLT2;                // external interrupt filter reg 2
    UINT32 EINTFLT3;                // external interrupt filter reg 3

    UINT32 EINTMASK;                // external interrupt mask reg
    UINT32 EINTPEND;                // external interrupt pending reg

    UINT32 GSTATUS0;                // external pin status
    UINT32 GSTATUS1;                // chip ID
    UINT32 GSTATUS2;                // reset status
    UINT32 GSTATUS3;                // inform register
    UINT32 GSTATUS4;                // inform register

	UINT32 DSC0;					// C0 - added by simon
	UINT32 DSC1;
	UINT32 DSC2;
	UINT32 MSLCON;

	UINT32 GPJCON;					// D0
	UINT32 GPJDAT;
	UINT32 GPJUDP;
	UINT32 PDA9;

	UINT32 GPKCON;					// E0
	UINT32 GPKDAT;

	UINT32 DATAPDEN;

	
	UINT32 PDA10;
    
	UINT32 GPLCON;					// F0
	UINT32 GPLDAT;
	UINT32 GPLUDP;
	UINT32 PDA11;

	UINT32 GPMCON;					// 100
	UINT32 GPMDAT;
	UINT32 GPMUDP;
	UINT32 PDA12;
} S3C2443_IOPORT_REG, *PS3C2443_IOPORT_REG;  

#endif